The present exemplary embodiments pertain to integrated circuit design, and, in particular, to avoiding coupled noise during global routing.
As computer speeds have increased, and semiconductor technology dimensions have decreased, coupled noise effects on timing have correspondingly worsened. In addition, newer semiconductor technologies employ reduced lithography dimensions. The smaller shape sizes have resulted in reduced spacing between wires, and increased capacitive coupling between nets within integrated circuits.
Advanced semiconductor technologies are becoming increasingly susceptible to coupled noise. Under the right circumstances of signal-to-signal synchronicity, a given amount of coupled noise energy results in a corresponding delay impact on signal timing. The probability that this change in delay will result in a timing violation increases as machine speeds increase and cycle times decrease.
Semiconductor chip (hereafter just “chip”) interconnects drastically affect the performance and function of advanced chips, with capacitances the most limiting factor. It is important to accurately predict and avoid factors that may negatively affect the performance or function of a chip.
Capacitive coupling and noise (i.e., crosstalk) must be contained for the chips to work with the desired performance and function. Coupling noise analysis methods often require lengthy extraction and simulations steps, and require the designer to iterate back over a design to correct problems found in analysis. Any effort to avoid noise while in the chip construction steps may prove to be very beneficial to the designer, by creating correct-by-construction circuits which do not require several iterations of analysis and fixup, thereby reducing the design cycle.